1. Technical Field
This invention relates to an improvement in a level conversion apparatus connected between a logic circuit of a first standard having a predetermined logic swing and a logic circuit of a second standard having a logic swing greater than that of the first standard, for converting a signal from the first standard logic circuit to the logic swing of a signal of the second standard, and more particularly to a level conversion apparatus enabling lowering of a source voltage level.
2. Description of the Background Art
The recent progress in semiconductor technology has led to development of logic integrated circuits of various standards ranging from relatively slow TTL (Transistor-Transistor Logic) to ECL (Emitter-Coupled Logic).
FIG. 10 is a block diagram showing an example of computer systems including TTL logic integrated circuits. Referring to this drawing, a bus line 1 has, connected thereto, a CPU 2, a main memory 3, a cache memory 4 and an input/output device 5 all formed of TTL elements, for example. External devices such as a printer 6 and a keyboard 7 are connected to the input/output device 5.
However, the CPU 2 and cache memory 4, for example, are sometimes replaced by a CPU 2' and a cache memory 4' formed of ECL elements to meet the need for high-speed processing. In this case, as shown in FIG. 11, level conversion apparatus 9 must be connected between the CPU 2' and bus line 1 and between the cache memory 4' and bus line 1, respectively. In other words, when using, in combination, ECL devices operable at a relatively high-speed and TTL devices which are relatively slow, it is necessary to match the levels of the two types of devices.
FIG. 12 is a block diagram showing an example where an ECL logic integrated circuit 8 and a TTL logic integrated circuit 10 are interconnected through a conventional level conversion apparatus 9. The ECL integrated circuit 8 is supplied with a source voltage VEE of -5.2 to -4.5 volts, and outputs a signal terminating at a resistor Rg of 50 ohms. This resistor Rg is supplied with a source voltage VTT of -2 volts. The ECL integrated circuit 8 has a high level (H) logic amplitude at -0.8 volts and a low level (L) logic amplitude at -1.6 volts. On the other hand, a source voltage VTL of +5 volts is connected to the TTL integrated circuit 10. The TTL integrated circuit 10 has a high level logic amplitude at 2.4 volts or more and a low level logic amplitude at 0.4 volts or less.
The level conversion apparatus 9 is supplied with the two source voltages VTL and VEE of +5 volts and -5 volts, and converts the ECL levels (H=-0.8 V, L=-1.6 V) into the TTL levels (H&gt;2.4 V, L&lt;0.4 V).
FIG. 13A is a block diagram of the above mentioned conventional level conversion apparatus 9. Referring to the figure this apparatus includes an input switching circuit A, a reference voltage generating circuit B, a control signal generating circuit E and output switching circuit C. The reference voltage generating circuit B receives the supply voltage V.sub.EE (-5 V) and generates reference voltages Vbb and Vcs. The reference voltages V.sub.bb and V.sub.cs are applied to the input switching circuit A.
The input switching circuit A is connected between the supply voltage V.sub.EE and the control signal generating circuit E, and it carries out switching operation upon reception of a signal V.sub.in from an ECL integrated circuit. More specifically, if the potential of the signal V.sub.in is higher than the potential of the reference voltage V.sub.bb, it turns on, and if the potential of the signal V.sub.in is lower than the potential of the reference voltage V.sub.bb, it turns off. The reference voltage V.sub.cs determines the amount of the current flowing to input switching circuit A when the input switching circuit A turns on.
The control signal generating circuit E generates a control signal for turning off the output switching circuit C in response to the switch-on signal from the input switching circuit A, and a control signal for turning on the output switching circuit C in response to a switch-off signal from the input switching circuit A.
The output switching circuit C is connected between the supply voltage V.sub.cc (5 V) and the ground potential and switches in response to two control signals from the control signal generating circuit E, and generates a signal V.sub.out of the TTL level.
FIG. 13B is a circuit diagram illustrating one example of the conventional level conversion apparatus 9. This apparatus is described in MELL INTEGRATED CIRCUITS DATA BOOK, 1971, published by Motorola. Referring to FIG. 13B, this level conversion circuit includes an ECL input terminal Vi, a TTL output terminal Vo, a source terminal Vcc supplied with 5 V, a source terminal VEE supplied with -5 V, and a ground terminal GND. Transistors Q21, Q22 and Q23 and a resistor R25 constitute an input switching circuit A. Transistors Q27 and Q28, diodes D27 and D25, and resistors R26, R27, R28 and R29 constitute a reference voltage generating circuit B which supplies voltages Vbb and Vcs to the input switching circuit A. The voltage Vbb is a reference voltage for determining a threshold level for input, and is set to a potential (-1.2 V) approximately midway between the high level and low level logic amplitudes of the ECL. The voltage Vcs is a reference voltage for determining a current level for the input switching circuit A, and is applied to the base of transistor Q23. Resistors R21 and R24 provide load resistances of the input switching circuit A, which are supplied to a totem pole type output circuit C composed of transistors Q25 and Q26 and a diode D23. A transistor Q24, resistors R22 and R23, and diodes D21 and 22 constitute a voltage clamping circuit D for regulating an upper limit of the voltage generated from the load resistor R24 of the input switching circuit A. The clamping circuit D, and resistors R21 and R24 constitute the control signal generating circuit E.
An operation of the level conversion apparatus shown in FIG. 13B will be described next.
Assume first that the ECL input terminal Vi is applied with high level (H=-0.8 V). Since the high-level signal (-0.8 V) applied to the input terminal Vi has a higher potential than Vbb, the transistor Q21 included in the input switching circuit A becomes conductive and the transistor Q22 becomes nonconductive. With the transistor Q21 becoming conductive, voltage is generated at opposite ends of the load resistor R21, thereby sufficiently lowering the base potential of the transistor Q25 of the output circuit C. The transistor Q25 becomes nonconductive in response to the lowering of this base voltage.
On the other hand, no current flows through the resistor R24 since the transistor Q22 is nonconductive. Consequently, the clamped voltage generated by the voltage clamping circuit D is applied to the transistor Q26 of the output circuit C, to render the transistor Q26 conductive. With the transistor Q26 becoming conductive, the output terminal Vo and ground terminal GND of the output circuit C are interconnected to output approximately 0 V (low level).
Assume next that the ECL input terminal Vi is applied with low level (L=-1.6 V). In response to the low level input, the transistor Q21 becomes nonconductive and the transistor Q22 conductive. With the transistor Q21 becoming nonconductive, no current flows through the input switching circuit A. Consequently, the base of the transistor Q25 of the output circuit C has a potential corresponding approximately to that of the source terminal Vcc, thereby rendering the transistor Q25 conductive. On the other hand, since the transistor Q22 is conductive, current flows from the input switching circuit A to the resistor R24, thereby sufficiently lowering the base potential of the transistor Q26 of the output circuit C. The transistor Q26 becomes nonconductive in response to the lowering of this base voltage. As a result, a high level signal is output from the output terminal Vo of the output circuit C. This high-level signal has a potential Vcc-2 Vbe, where Vbe is a forward voltage of the transistor Q25 or diode D23, whose value is about 0.8 V. If a load resistor is connected between the output terminal Vo and ground terminal GND, the output voltage will be about 3.4 V. If this is a capacitive load such as a capacitor, a potential on the order of 5 V will be output.
The conventional ECL-TTL level conversion circuit as constructed above has the drawback of large power consumption since the relatively high voltages of +5 V and about -5 V are used as source voltages for application to the level conversion circuit.
The source voltages may be lowered to eliminate the drawback of power consumption. However, since the totem pole type output circuit is used in the conventional circuit, at least 3 volts must be applied as the source voltage to the source terminal Vcc. The potential supplied to the source terminal VEE must be -3 V or less to generate the threshold voltage Vbb for the input switching circuit A and the threshold voltage Vcs for determining the current level.
FIG. 14 is a block diagram showing level conversion apparatus receiving data of plural bits. Referring to the figure, this level converting apparatus is different from the level converting apparatus of FIG. 13A in that a plurality of input switching circuits A, control signal generating circuits E and output switching circuits C are provided corresponding to the plurality of bits. More specifically, in order to receive a plurality of bit signals from the ECL logic integrated circuit, only the reference voltage generating circuit B may be used commonly, while the other circuits A, C and E must be provided in the number corresponding to the number of bits. However, each of the other circuits A, C and E includes a large number of elements and, if the number of such circuits is increased to correspond to the number of bits, the circuit construction will become complicated and require an enlarged substrate area.